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? e89x38g13-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage av dd , dv dd 7v input voltage (all pins) v in v dd +0.5 to v ss ?.5 v output current i out 15 ma storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss 4.75 to 5.25 v reference input voltage v ref 2.0 v clock pulse width tpw 1 ,tpw 0 11.2 ns (min) to 1.1 s (max) operating temperature topr ?0 to +85 ? description the CXD1171M is a 8-bit 40 mhz high speed d/a converter. the adoption of a current output system reduces power consumption to 80 mw (200 ? load at 2 vp-p output). this ic is suitable for digital tv and graphic display applications. features resolution 8-bit max. conversion speed 40msps non linearity error within 0.25 lsb low glitch noise ttl cmos compatible input +5 v single power supply low power consumption 80 mw (200 ? load at 2 vp-p output) function 8-bit 40 mhz d/a converter structure silicon gate cmos ic 8-bit 40msps high speed d/a converter 24 pin sop (plastic) CXD1171M
? CXD1171M block diagram and pin configuration 6msb's current cells latches decoder 19 20 21 22 23 24 clock generator 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 current cells (for full scale) bias voltage generator decoder 2lsb's current cells (lsb) d0 d1 d2 d3 d4 d5 d6 (msb) d7 blk dv ss vb clk dv dd dv dd av dd io io av dd av dd vg vref iref av ss dv ss
3 CXD1171M pin description and i/o pins equivalent circuit 1 to 8 9 11 12 10, 13 14 d0 to d7 blk vb clk dv ss av ss i i o i no. symbol i/o equivalent circuit description dv dd dv ss to 8 1 dv dd dv ss 9 dv dd dv ss dv dd 11 dv dd dv ss 12 digital input. d0 (lsb) to d7 (msb) d0 and d1 have a pull-down resistor. blanking input. this is synchronized with the clock signal. no signal at h (output 0 v). output condition at l . connect a capacitor of about 0.1 f. clock input. digital ground. analog ground.
4 CXD1171M 15 16 17 18, 19, 22 20 21 23, 24 iref vref vg av dd io io dv dd o i o o no. symbol i/o equivalent circuit description av ss av ss av dd av dd av ss av dd av dd 15 16 17 av dd av ss av dd av ss 20 21 set full-scale output value. connect a capacitor of about 0.1 f. analog power supply. current output. voltage output can be obtained by connecting a resistance. inverted current output. normally connected to analog gnd. digital power supply. connect a resistor r ir 16 times against the output resistance value r out connected to pin 20 (io).
5 CXD1171M electrical characteristics measurement circuit analog input resistance measurement circuit digital input current CXD1171M +5.25v av dd , dv dd av ss , dv ss v a } electrical characteristics (f clk =40 mhz, av dd =dv dd =5 v, r out =200 ? , v ref =2.0 v, ta=25 c) item resolution conversion speed integral non-linearity error differential non-linearity error output full-scale voltage output full-scale current output offset voltage glitch energy supply current analog input resistance input capacitance digital input voltage digital input current setup time hold time propagation delay time symbol n f clk e l e d v fs i fs v os ge i dd r in c i v ih v il i ih i il t s t h t pd measurement conditions av dd =dv dd =4.75 to 5.25 v ta= 40 to 85 c endpoint when d0 to d7=00000000 input r out =75 ? when 14.3 mhz color bar data input v ref av dd =dv dd =4.75 to 5.25 v ta= 20 to +75 c av dd =dv dd =4.75 to 5.25 v d0, d1 ta= 20 to +75 c d2 to 7, blk, clk r out =75 ? r out =75 ? min. 0.5 0.5 0.25 1.9 13 1 2.4 5 5 5 10 typ. 8 2.0 10 30 14.5 10 max. 40 1.3 0.25 2.1 15 1 16 9 0.8 240 5 unit bit msps lsb lsb v ma mv pv s ma m ? pf v a ns ns ns
6 CXD1171M maximum conversion speed measurement circuit clk 40mh z square wave clk 0.1 200 oscilloscope blk vb io vg vref iref 1k avss 0.1 3.3k av dd 8 9 11 12 15 16 17 20 d7 d0 (lsb) 8bit counter with latch 2v 1 2 dc characteristics measurement circuit clk 40mh z square wave clk 0.1 200 blk vb io vg vref iref 1k avss 0.1 3.3k av dd 8 9 11 12 15 16 17 20 d7 d0 (lsb) dvm 2v controller 2 1 propagation delay time measurement circuit clk 10mh z square wave clk 0.1 200 oscilloscope blk vb io vg vref iref 1k avss 0.1 3.3k av dd 8 9 11 12 15 16 17 20 d7 d0 (lsb) frequency demultiplier 2 1 clk 1mh z square wave clk 0.1 75 oscilloscope blk vb io vg vref iref 1k avss 0.1 1.2k av dd 8 9 11 12 15 16 17 20 d7 d0 (lsb) 8bit counter with latch 1v delay controller delay controller 2 1 setup time hold time measurement circuit glitch energy }
7 CXD1171M operation timing chart t pw1 t pw0 aa aa aa aa aa aa aaa aaa aaa aa aa aa t s t h t s t h t s t h t pd t pd t pd clk data d/a out 2v 100% 50% 0% application circuit dv dd av dd 200 0.1 2v 0.1 1k 3.3k dgnd d/a out agnd 19 20 21 22 23 24 13 14 15 16 17 18 8bit digital input 3 4 5 6 7 8 9 10 11 12 (lsb) 2 1 i/o chart (when full-scale output voltage at 2.00 v) input code msb lsb 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 output voltage 2.0 v 1.0 v 0 v application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
8 CXD1171M notes on operation how to select the output resistance the CXD1171M is a d/a converter of the current output type. to obtain the output voltage connect the resistance to the current output pin io. for specifications we have: output full scale voltage v fs = 1.9 to 2.1 [v] output full scale current i fs = less than 15 [ma] calculate the output resistance value from the relation of v fs = i fs r out . also, 16 times resistance of the output resistance is connected to reference current pin iref. in some cases, however, this turns out to be a value that does not actually exist. in such a case a value close to it can be used as a substitute. here please note that v fs becomes v fs = v ref 16r out /r ir . r out is the resistance connected to io while r ir is connected to iref. increasing the resistance value can curb power consumption. on the other hand glitch energy and data settling time will inversely increase. set the most suitable value according to the desired application. phase relation between data and clock to obtain the expected performance as a d/a converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. be sure to satisfy the provisions of the setup time ( t s ) and hold time ( t h ) as stipulated in the electrical characteristics. power supply and ground to reduce noise effects separate analog and digital systems in the device periphery. for the power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 f, as close as possible to the pin. latch up av dd and dv dd have to be common at the pcb power supply source. this is to prevent latch up due to voltage difference between av dd and dv dd pins when power supply is turned on. io pin the io pin is the inverted current output pin described in the pin description. the sum of the currents output from the io pin and the io pin becomes the constant value for any input data. however, the performances such as the linearity error of the io pin output current is not guaranteed.
9 CXD1171M latch up prevention the CXD1171M is a cmos ic which requires latch up precautions. latch up is mainly generated by the lag in the voltage rising time of av dd (pins 18, 19 and 22) and dv dd (pins 23 and 24), when power supply is on. 1. correct usage a. when analog and digital supplies are from different sources b. when analog and digital supplies are from a common source (i) (ii) +5v av dd +5v av ss dv ss av ss dv ss av dd dv dd CXD1171M dv dd digital ic 18 19 22 24 10 13 14 23 cc +5v av ss dv ss av ss dv ss av dd dv dd CXD1171M dv dd digital ic 18 19 22 24 10 13 14 23 c c +5v av ss dv ss av ss dv ss av dd dv dd CXD1171M dv dd digital ic 18 19 22 24 10 13 14 23 c c
10 CXD1171M 2. example when latch up easily occurs a. when analog and digital supplies are from different sources b. when analog and digital supplies are from common source (i) (ii) +5v av dd +5v av ss dv ss av ss dv ss av dd dv dd CXD1171M dv dd digital ic c 18 19 22 24 10 13 14 23 c +5v av ss dv ss av ss dv ss av dd dv dd CXD1171M dv dd digital ic av dd 18 19 22 24 10 13 14 23 c c +5v av ss dv ss av ss dv ss av dd dv dd CXD1171M dv dd digital ic av dd 18 19 22 24 10 13 14 23 c
11 CXD1171M 1.0 0 1.0 2.0 reference voltage vs. output full scale voltage reference voltage v ref [v] output full scale voltage v fs [v] 2.0 0255075 25 0 output full-scale voltage v fs [v] 1.9 2.0 ambient temperature vs. output full scale voltage ambient temperature ta [ c] 100 100 output resistance vs. glitch energy output resistance r out [ ? ] glitch energy ge [pv s] 200 200 av dd =dv dd = 5.0v v ref =2.0v r out =200 ? r ir =3.3k ? av dd =dv dd =5.0v v ref =2.0v r ir 16r out ta=25 c av dd =dv dd =5.0v r out =200 ? r ir =3.3k ? ta=25 c 0
sony code eiaj code jedec code m package structure molding compound lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 24pin sop (plastic) 15.0 0.1 + 0.4 1 12 13 24 0.45 0.1 5.3 0.1 + 0.3 7.9 0.4 0.2 0.05 + 0.1 0.5 0.2 0.1 0.05 + 0.2 0.15 1.85 0.15 + 0.4 6.9 0.24 sop-24p-l01 sop024-p-0300 0.3g 1.27 package outline unit : mm CXD1171M 12
13 CXD1171M sony corporation sony code eiaj code jedec code m package structure molding compound lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 24pin sop (plastic) 15.0 0.1 + 0.4 1 12 13 24 0.45 0.1 5.3 0.1 + 0.3 7.9 0.4 0.2 0.05 + 0.1 0.5 0.2 0.1 0.05 + 0.2 0.15 1.85 0.15 + 0.4 6.9 0.24 sop-24p-l01 sop024-p-0300 0.3g 1.27 package outline unit : mm lead specifications item lead material copper alloy lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec.

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